(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device employing partially depleted-silicon on insulator (PD-SOI) substrate and a method of manufacturing the same.
(b) Description of the Related Art
Generally, an SOI substrate employs a silicon layer formed over an insulating layer on a silicon wafer, to have a structure in which the insulating layer is buried within the silicon layers.
Therefore, in the case of manufacturing a metal oxide silicon (MOS) transistor in this SOI substrate, body layers of the MOS transistor are isolated by the buried insulating layer and an isolating layer, and as a result, the speed and the integration density of the MOS transistor are improved.
This SOI substrate is classified into a fully depleted type (FD) and a partially depleted type (PD) based on the thickness of the silicon layer.
First, a MOS transistor employing the FD-SOI substratewill be described with reference to a FIG. 1.
As shown in FIG. 1, isolating layers 11 are formed in a silicon layer 10c of a FD-SOI substrate 10 employing the silicon layer 10c that is formed relatively thinly over a buried insulating layer 10b on a silicon wafer 10a to be in vertical contact with the buried insulating layer 10b, and a body layer 12 of a P well is formed in the silicon layer 11c between the isolating layers 11. A gate insulating layer 13 and a gate electrode 14 are sequentially formed on the body layer 12. LDD (Lightly Doped Drain) regions 15 in which low concentration impurities, for example N− are ion-implanted, are formed within the body layer 12 of both sides of the gate electrode 14 to be in contact with the buried insulating layer 10b. A spacer 16 of an insulating material is formed on the side wall of the gate electrode 14. Source and drain regions 17 in which high concentration impurities, for example N+ are ion-implanted, are formed within the body layer 12 of both sides of the spacer 16 to be in contact with the buried insulating layer 10b. 
Thus, in the MOS transistor employing the FD-SOI substrate, as the LDD regions 15 and the source and drain regions 17 are formed within the body layer 12 to be in contact with the buried insulating layer 10b by the thin silicon layer 10c, a depletion layer is fully formed in the body layer 12 when a back bias voltage is not applied to the body layer 12.
Next, a MOS transistor employing the PD-SOI substratewill be described with reference to a FIG. 2.
As shown in FIG. 2, isolating layers 21 are formed in a silicon layer 20c of a PD-SOI substrate 20 employing the silicon layer 20c that is formed relatively thickly over a buried insulating layer 20b to be in vertical contact with the buried insulating layer 20c, and a body layer 22 of a P well is formed in the silicon layer 20c between the isolating layers 21. A gate insulating layer 23 and a gate electrode 24 are sequentially formed on the body layer 22. LDD regions 25 in which low concentration impurities, for example N− impurities are ion-implanted, are formed within the body layer 22 of both sides of the gate electrode 24 to be separated from the buried insulating layer 20b. A spacer 26 of an insulating material is formed on the side wall of the gate electrode 24. Source and drain regions 27 in which high concentration impurities, for example N+ impurities are ion-implanted, are formed within the body layer 22 of both sides of the spacer 26 to be separated from the buried insulating layer 20b. 
Thus, in the MOS transistor employing the PD-SOI substrate, as the LDD regions 25 and the source and drain regions 27 are formed within the body layer 22 to be separated from the buried insulating layer 20 by the thick silicon layer 20c, a depletion layer is partially formed in the body layer 22 when a back bias voltage is not applied to the body layer 22.
Therefore, a floating body region exists under a channel region, so that a floating body effect occurs.
This floating body effect accumulates holes generated by impact ionization of electrons around a drain region in the floating body region, to increase the potential of the body layer and to lower a potential barrier between the source region and the body layer, thereby decreasing a threshold voltage and increasing a drain current.
Furthermore, if the potential of the body layer will be increased above 0.6V, a parasitic bipolar transistor formed by the source region/the body layer/the drain region is turned on, to break down the transistor.
In addition, if the accumulated holes are combined with a portion of electrons consisting of a driving current of the transistor when a specific driving current flows, leakage current and operation errors occur.
To preventing the floating body effect, the following three methods are proposed.
A first method prevents the body floating effect by forming a body contact on the MOS transistor and connecting it to ground. However, since a potential of the body layer is maintained at 0V and a voltage of the source region increases in the case of employing the body contact to the MOS transistor, a reverse bias is applied to the source region and the body region respectively, to increase a threshold voltage and to decrease a drain current, thereby deteriorating the performance of the MOS transistor. Furthermore, since the MOS transistor requires an additional region to form the body contact, there is a problem that its size increases
A second method prevents the body floating effect by forming point defects as a life time killer in the source and drain regions. However, as Ar or Ge ions are implanted into the silicon layer by ion-implantation to form the point defects, there is problem in that the surface of the silicon layer is damaged by the ions.
A third method prevents the body floating effect by forming a narrow band gap source in the source and drain regions using a SiGe epitaxial process. However, there is problem in that it is difficult to perform the epitaxial process.